This invention relates to electrostatic discharge protection circuits (ESD protection circuits) for integrated circuit chips.
Basically, in an integrated circuit chip, metal signal pads are provided to which discrete wires are bonded to thereby provide a means for sending input signals to the chip and receiving output signals from the chip. Those signals, under normal operating conditions, are restricted to lie within a certain voltage range. Typically, that voltage range is within .+-.5 volts. However, due to electrostatic charge, the voltage on the signal pads can, for a short time period (e.g., a few nanoseconds), become 1,000 volts or higher.
Such electrostatic charge usually accumulates first on one's body. A simple circuit, which approximates the equivalent circuit for the human body, is a 100 picofarad capacitor C in series with a 1,500 ohm resistor R. Thus, by accumulating a charge Q of just 1.times.10.sup.-7 Coulumb's on the capacitor, the voltage V across it becomes 1,000 volts (Q=VC). This amount of charge, either positive or negative, can readily be accumulated by a person in various ways, such as by walking in shoes with rubber soles across a rug. That charge will then be transferred from the person to a signal pad on a chip if the person contacts either the pad, or a wire to which the pad is connected.
After this charge is transferred to the signal pad, it can flow from the pad as a large current to any transistors which are connected on the chip to the pad. And this large current can burn out the transistors. So to address this problem, various static discharge protection circuits have been proposed in the prior art. See, for example, U.S. Pat. Nos. 4,481,421 and 4,605,980, and 4,686,602. However, the protection circuits of these patents, and others, have a serious deficiency.
That deficiency, the present inventors have found, is that the conductance from each signal pad to its transistor is fixed at some predetermined level. This is a problem because if the conductance is high, then any electrostatic charge on the signal pad will pass right to the pad's transistor (just like a normal input signal) and burn out the transistor. Burnout occurs even if a Zener diode is placed in parallel with the path to divert charge from the transistor since the diode will have some resistance, and the charge will tend to follow the high conductance path.
Conversely, if the conductance is lowered by adding a resistor in series between the signal pad and its transistor, then less electrostatic charge will pass from the signal pad to its transistor. But then, normal input signals will also pass more slowly to the transistor. This signal delay will occur because some parasitic capacitance is always present in the path from the signal pad to its transistor, and that capacitance together with the added resistor will act as a low pass filter. And, in high speed electronic systems such as digital computers, signal delay must be minimized.
Accordingly, a primary object of the invention is to provide an improved static discharge protection circuit for integrated circuits in which the above problem is overcome.